1. Field of the Invention
Embodiments of the present invention relate to a semiconductor device and a method of fabricating the same, and more particularly, to an interconnection structure having an oxygen trap pattern in a semiconductor device, and a method of fabricating the same.
2. Description of the Related Art
Generally, semiconductor devices include an integrated circuit composed of discrete devices such as transistors, resistors and capacitors. The discrete devices may be electrically connected to each other through interconnections provided in an interlayer insulating layer. As the semiconductor devices are highly integrated, the size of the interconnections is also downscaled. Due to such a trend, the interconnections require various characteristics. One of the required characteristics is high conductivity. High conductivity helps to prevent signal delay typically caused by high resistance of the interconnection. For this reason, recent trends are toward the use of interconnections that are formed of metal, for example, aluminum or tungsten.
FIGS. 1A to 1C are cross-sectional views illustrating a method of fabricating a conventional interconnection structure.
Referring to FIG. 1A, a lower interlayer insulating layer 12 may be formed on a semiconductor substrate 10. A lower metal layer and a capping layer may be sequentially stacked on the lower interlayer insulating layer 12. The lower metal layer may be formed of aluminum or an aluminum alloy. Further, the capping layer may be formed of titanium nitride. Subsequently, the capping layer and the lower metal layer may be continuously patterned so that a lower metal layer pattern 22 and a capping layer pattern 24 can be formed. As a result, a lower metal interconnection 20 including the lower metal layer pattern 22 and the capping layer pattern 24, which are sequentially stacked, may be formed.
Then, an upper interlayer insulating layer 26 may be formed on the entire surface of the semiconductor substrate 10 having the lower metal interconnection 20. A photoresist pattern 28 having an opening exposing a predetermined region of the upper interlayer insulating layer 26 may be formed. The upper interlayer insulating layer 26 may be etched using the photoresist pattern 28 as an etch mask to form a via contact hole 30 exposing the capping layer pattern 24.
Referring to FIG. 1B, the photoresist pattern 28 is removed. The photoresist pattern 28 may be removed by an ashing process. The ashing process may be performed using an oxygen gas 32 or an ozone gas in addition to plasma to remove the photoresist pattern 28. The oxygen gas 32 penetrates into the exposed capping layer pattern 24. If the capping layer pattern 24 is formed of a titanium nitride layer, the titanium nitride layer 24 may have vertical grains. Accordingly, the oxygen gas 32 may penetrate into an interface between the titanium nitride layer 24 and the lower metal layer pattern 22 along grain boundaries of the titanium nitride layer 24. The oxygen gas 32 diffuses into the layers formed at both sides of the interface, thereby forming an interfacial oxide layer 34 such as an aluminum titanium oxynitride (AlTiON) layer at the interface. The interfacial oxide layer 34 is a quaternary oxide layer, which generally has high specific resistance.
Referring to FIG. 1C, an upper metal layer may be formed on the semiconductor substrate 10 having the via contact hole 30. The upper metal layer may form a contact plug 36, which is electrically in contact with the lower metal interconnection 20 as a result of the upper metal layer filling the via contact hole 30. Then, the upper metal layer disposed on the upper interlayer insulating layer 26 may be patterned to form an upper metal interconnection 38.
According to the conventional technique, a contact resistance between the contact plug 36 and the lower metal interconnection 20 increases due to the interfacial oxide layer 34. Accordingly, current flowing from the upper metal interconnection 38 to the lower metal interconnection 20 is hindered by the interfacial oxide layer 34. Further, in a subsequent annealing process, the oxygen remaining in the titanium nitride layer 24 may diffuse to the interface causing the interfacial oxide layer 34 to be formed thicker. Due to the high resistance of the interfacial oxide layer 34, the current between the upper and lower metal interconnections 38 and 20 may be interrupted. In addition, resistance of the lower metal interconnection 20 itself may also increase. Consequently, the reliability of the semiconductor device is degraded.